1. Field of the Invention
The present invention pertains to a fast electronic circuit designed to process information in a signal-processing chain. More precisely, it pertains to a sample-and-hold circuit which is preferably made in the form of an integrated circuit, on silicon or fast-acting materials of the group III-V, such as GaAs for example.
The scope of this sample-and-hold circuit ranges from relatively low frequencies (a few megahertz) to about 1 GHz. This sample-and-hold circuit has been developed and perfected for high frequencies, but its design does not prevent the device from being used at lower frequencies. The device is of the diodes bridge type.
2. Description of the Prior Art
A sample-and-hold circuit is used in a signal-processing chain such as the one shown in FIG. 1. There are two possible ways to transform the analog signal given by a sensor 1 into a digitalized signal. The first way is to transform the analog signal with an analog-digital converter (ADC) 2 and then to periodically memorize the digital signals given by the ADC. The output of the flip-flop 3 gives a digital signal at 4, in a certain number of bits, depending on the precision sought.
The second way is to interpose a sample-and-hold circuit 5 between the sensor 1 and the ADC 2. This sample-and-hold circuit can be likened to a switch followed by a capacitor: when the switch is open, the voltage at its output terminal is memorized in the capacitor for a period of time which, ideally, depends only on the clock frequency that controls the opening and closing of the switch but which, in practice, depends on the value of the storage capacity and on the constraints (current leakages) related to the technology used. The voltage of the analog signal, coming from the sensor 1, is sampled by the sample-and-hold circuit 5 and digitalized by the analog-digital converter 2.
Sample-and-hold circuits are valuable because of their simplicity, which favours monolithic integration. However, the speed and precision of present-day models is below that of the best ADCs of the flash type. The limitations arise chiefly from stray signals induced by the clock signal at the holding instant and by the input signal in the "hold" mode. The choice of a high storage capacity to reduce these phenomena would imply a reduction of the sampling frequency, namely a reduction in the width of the pass-band. Thus there is a conflict of goals between speed and precision.
These disadvantages have two causes. Firstly, as we shall see further below, sample-and-hold circuits of the prior art are controlled by two switches. It is difficult to synchronize the two clock switches which are subjected to different potential sweeps. In practice, such synchronization requires two separate commands which are not perfectly synchronized. Secondly, a difference in potential sweeps at the terminals of the diodes bridge, during the hold mode, causes an input of voltage into the bridge, depending on the value of the input signal.